The present disclosure relates generally to chip manufacturing, and more particularly to methods, systems and computer program products for generating functional test patterns for diagnostics, characterization and manufacture test.
The generation of effective functional test patterns is a difficult and complex problem encountered at device final test. These functional test patterns need to be equivalent to system exercisers executed in a system mission mode environment. Final tests are a critical step to ensure system design verification, functionality and acceptable device quality level at system integration.
The rapid densification of VLSI devices, incorporating complex functions operating at extreme circuit performance, has driven designs towards integrating many diverse functional macros or cores within these large chips. These macros range from autonomous processor cores with large cache arrays occupying relatively large portions of the chip's real estate, to a multitude of small arrays used as register stacks, trace arrays, content addressable memories, phase locked loops (PLL), and many other special purpose logic functions. These highly integrated circuit functions, in conjunction with state-of-the-art semiconductor technology advances, results in several test and diagnostic problems that have driven the generation of functional test patterns toward system equivalent functional test execution. The functional test patterns need to be used during manufacturing final tests of the device on a generic automatic test equipment (ATE) system, and these functional test patterns need to effectively emulate the execution of functional exercisers in a system mission equivalent environment.
Therefore, heretofore unaddressed needs still exist in the art to address the aforementioned deficiencies and inadequacies.